THC63LVDF84B/thc63lvdf64b_rev2.0 copyright 2001-2003 thine electronics, inc. all rights reserved 1 thine electronics, inc. THC63LVDF84B/thc63lvdf64b lvds 24bit/18bit color host-lcd panel interface receiver general description the THC63LVDF84B/thc63lvdf64b receiver sup- ports wide vcc range(2.5~3.6v). at single 2.5v sup- ply, the THC63LVDF84B/thc63lvdf64b reduces emi and power consumption. the THC63LVDF84B receiver convert the four lvds(low voltage differential signaling) data streams back into 28bits of cmos/ttl data with falling edge clock. at a transmit clock frequency of 85mhz, 28bits of rgb data and 4bits of lcd timing and control data (hsync, vsync, cntl1, cntl2) are transmitted at a rate of 2.3gbps. also the thc63lvdf64b receiver convert the three lvds data streams back into 21bits of cmos/ttl data with falling edge clock. at a transmit clock frequency of 85mhz, 21bits of rgb data and 4bits of lcd timing and control data (hsync, vsync, cntl1, cntl2) are transmitted at a rate of 1.78gbps. features ? wide vcc range: 2.5~3.6v ? wide dot clock range: 20-85mhz suited for vga, svga, xga and sxga (vcc=3.0~3.6v) ? wide dot clock range: 20-70mhz suited for vga, svga, xga and sxga (vcc=2.5v~3.6v) ? pll requires no external components ? rx power consumption < 80mw @vcc 2.5v, 65mhz grayscale ? power-down mode ? low profile 56 lead or 48 lead tssop package ? pin compatible with thc63lvdf84a/f64a block diagram lvds to ttl parallel pll ra +/- rb +/- rc +/- rd +/- rclk +/- /pdwn ra0-6 rc0-6 rd0-6 receiver (20 to 85mhz) cmos/ttl rb0-6 output clock (lvds) 20 to 85mhz data (lvds) (140-595mbit/on each lvds channel) 7 7 7 7 clock out lvds to ttl parallel pll ra +/- rb +/- rc +/- rclk +/- /pdwn ra0-6 rc0-6 receiver (20 to 85mhz) cmos/ttl rb0-6 output clock (lvds) 20 to 85mhz data (lvds) 7 7 7 clock out thc63lvdf64b THC63LVDF84B
copyright 2001-2003 thine electronics, inc. all rights reserved 2 thine electronics, inc. THC63LVDF84B/thc63lvdf64b _rev2.0 pin out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 rc3 rd6 rc4 gnd rc5 rc6 rd0 lvdsgnd ra- ra+ rb- rb+ lvdsvcc lvdsgnd rc- rc+ rclk- rclk+ rd- rd+ lvdsgnd pllgnd pllvcc pllgnd /pdwn clkout ra0 gnd vcc rc2 rc1 rc0 gnd rb6 rd5 rd4 vcc rb5 rb4 rb3 gnd rb2 rd3 rd2 vcc rb1 rb0 ra6 gnd ra5 rd1 ra4 ra3 vcc ra2 ra1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 rc3 rc4 gnd rc5 rc6 n/c lvdsgnd ra- ra+ rb- rb+ lvdsvcc lvdsgnd rc- rc+ rclk- rclk+ lvdsgnd pllgnd pllvcc pllgnd /pdwn clkout ra0 vcc rc2 rc1 rc0 gnd rb6 vcc rb5 rb4 rb3 gnd rb2 vcc rb1 rb0 ra6 gnd ra5 ra4 ra3 vcc ra2 ra1 gnd 41 42 43 44 45 46 47 48 THC63LVDF84B thc63lvdf64b
copyright 2001-2003 thine electronics, inc. all rights reserved 3 thine electronics, inc. THC63LVDF84B/thc63lvdf64b _rev2.0 THC63LVDF84B pin description thc63lvdf64b pin description pin name pin # type description ra+, ra- 9, 10 lvds in lvds data inputs rb+, rb- 11, 12 lvds in rc+, rc- 15, 16 lvds in rd+, rd- 19, 20 lvds in rclk+, rclk- 17, 18 lvds in lvds clock inputs ra0~ra6 27,29,30,32,33,35,37 out pixel data outputs rb0~rb6 38,39,43,45,46,47,51 out rc0~rc6 53,54,55,1,3,5,6 out rd0~rd6 7,34,41,42,49,50,2 out clkout 26 out pixel clock output /pdwn 25 in h: normal operation l: power down (all outputs are pulled to ground ) vcc 31,40,48,56 power power supply pins for ttl outputs and digital circuitry gnd 4,28,36,44,52 ground ground pins for ttl outputs and digital circuitry lvdsvcc 13 power power supply pin for lvds inputs lvdsgnd 8,14,21 ground ground pins for lvds inputs pllvcc 23 power power supply pin for pll circuitry pllgnd 22,24 ground ground pins for pll circuitry pin name pin # type description ra+, ra- 8,9 lvds in lvds data inputs rb+, rb- 10,11 lvds in rc+, rc- 14,15 lvds in rclk+, rclk- 16,17 lvds in lvds clock inputs ra0~ra6 24,26,27,29,30,31,33 out pixel data outputs rb0~rb6 34,35,37,39,40,41,43 out rc0~rc6 45,46,47,1,2,4,5 out clkout 23 out pixel clock output /pdwn 22 in h: normal operation l: power down ( all outputs are pulled to ground) vcc 28,36,42,48 power power supply pins for ttl outputs and digital circuitry gnd 3,25,32,38,44 ground ground pins for ttl outputs and digital circuitry lvdsvcc 12 power power supply pin for lvds inputs lvdsgnd 7,13,18 ground ground pins for lvds inputs pllvcc 20 power power supply pin for pll circuitry pllgnd 19,21 ground ground pins for pll circuitry
copyright 2001-2003 thine electronics, inc. all rights reserved 4 thine electronics, inc. THC63LVDF84B/thc63lvdf64b _rev2.0 electrical characteristics cmos/ttl dc specifications vcc = 2.5v ~ 3.6v, ta = -10 ~ +70 lvds receiver dc specifications vcc = 2.5v ~ 3.6v, ta = -10 ~ +70 absolute maximum ratings 1 supply voltage (vcc) -0.3 to +4v cmos/ttl input voltage -0.3 to (vcc + 0.3v) cmos/ttl output voltage -0.3v to (vcc + 0.3v) lvds receiver input voltage -0.3v to (vcc + 0.3v) junction temperature +125 storage temperature range -55 to +150 resistance to soldering heat +260 /10sec maximum power dissipation@25 0.5w symbol parameter conditions min. typ. max. units v ih high level input voltage 2.0 vcc v v il low level input voltage gnd 0.8 v v oh1 high level output voltage vcc= 3.0v ~ 3.6v i oh = -4ma 2.4 v v ol1 low level output voltage vcc = 3.0v ~ 3.6v i ol = 4ma 0.4 v v oh2 high level output voltage vcc= 2.5v ~ 3.0v i oh = -2ma 2.1 v v ol2 low level output voltage vcc = 2.5v ~ 3.0v i ol = 2ma 0.4 v i in input current ua symbol parameter conditions min. typ. max. units v th differential input high threshold voc = +1.2v 100 mv v tl differential input low threshold -100 mv i in input current v in = +2.4v/0v vcc = 3.6v ua 1. ?absolute maximum ratings? are those valued beyond which the safety of the device can not be guaranteed. they are not meant to imply that the device should be operated at these limits. the tables of ?electrical characteristics? specify conditions for device operation. c c 0v vin vcc 10 c c 10 c c c c c
copyright 2001-2003 thine electronics, inc. all rights reserved 5 thine electronics, inc. THC63LVDF84B/thc63lvdf64b _rev2.0 supply current vcc = 2.5v ~ 3.6v, ta = -10 ~ +70 symbol parameter condition(*) typ. max. units i rccg receiver supply current 16grayscale pattern cl=8pf, vcc=3.3v f = 65mhz 41 53 ma f = 85mhz 52 64 ma cl=8pf, vcc=2.5v f = 65mhz 30 42 ma i rccw receiver supply current worst case pattern cl=8pf, vcc=3.3v f = 65mhz 72 94 ma f = 85mhz 84 96 ma cl=8pf, vcc=2.5v f = 65mhz 42 64 ma i rccs receiver power down supply current /pdwn = l 10 a c c clkin rx0 rx1 rx2 rx3 rx4 rx5 rx6 16 gray scale pattern clkin even rxin odd rxin worst case pattern
copyright 2001-2003 thine electronics, inc. all rights reserved 6 thine electronics, inc. THC63LVDF84B/thc63lvdf64b _rev2.0 switching characteristics vcc= 2.5v ~ 3.6v, ta = -10 ~ +70 symbo l parameter min. typ. max. unit s t rcp clk out period vcc = 3.0 - 3.6v 11.76 t 50.0 ns vcc = 2.5 - 3.6v 14.28 t 50.0 ns t rch clk out high time 4t/7 ns t rcl clk out low time 3t/7 ns t rcd rclk +/- to clk out delay 5t/7 ns t rs ttl data setup to clk out 0.35t-0.3 ns t rh ttl data hold from ckl out 0.45t-1.6 ns t tlh ttl low to high transition time 2.0 3.0 ns t thl ttl high to low transition time 1.8 3.0 ns t rip1 input data position0 (t = 11.76ns) -0.4 0.0 0.4 ns t rip0 input data position1 (t = 11.76ns) t/7-0.4 t/7 t/7+0.4 ns t rip6 input data position2 (t = 11.76ns) 2t/7-0.4 2t/7 2t/7+0.4 ns t rip5 input data position3 (t = 11.76ns) 3t/7-0.4 3t/7 3t/7+0.4 ns t rip4 input data position4 (t = 11.76ns) 4t/7-0.4 4t/7 4t/7+0.4 ns t rip3 input data position5 (t = 11.76ns) 5t/7-0.4 5t/7 5t/7+0.4 ns t rip2 input data position6 (t = 11.76ns) 6t/7-0.4 6t/7 6t/7+0.4 ns t rpll phase lock loop set 10.0 ms c c ac timing diagrams ttl output 8pf 20% 80% 20% 80% t tlh t thl ttl output ttl output load
copyright 2001-2003 thine electronics, inc. all rights reserved 7 thine electronics, inc. THC63LVDF84B/thc63lvdf64b _rev2.0 ac timing diagrams v diff = 0v rx+/- rx6 rx5 rx4 rx3 rx2 rx1 rx0 v diff = 0v t rip2 t rip3 t rip4 t rip5 t rip6 t rip0 t rip1 t rcd rclk+ t rch t rcl t rcp clkout t rs t rh data valid rx0 - rx6 vcc/2 vcc/2 vcc/2 vcc/2 vcc/2 vcc/2 note: 1) vdiff = (ra+) - (ra-), ...... (rclk+) - (rclk-) data valid
copyright 2001-2003 thine electronics, inc. all rights reserved 8 thine electronics, inc. THC63LVDF84B/thc63lvdf64b _rev2.0 ac timing diagrams phase lock loop set time vcc t rpll /pdwn 3.6v rclk+/- clkout vcc/2 vcc/2 vcc/2
copyright 2001-2003 thine electronics, inc. all rights reserved 9 thine electronics, inc. THC63LVDF84B/thc63lvdf64b _rev2.0 package 56 lead molded thin shrink small outline package, jedec (1.0) 0.10 0.05 1.2 max 0.20 typ 0.50 typ 8.1 0.1 4.05 128 6.1 0.1 14.0 0.1 29 56 unit : millimeters 48 lead molded thin shrink small outline package, jedec (1.0) 0.10 0.05 1.2 max 0.20 typ 0.50 typ 8.1 0.1 4.05 124 6.1 0.1 12.5 0.1 25 48 unit : millimeters
copyright 2001-2003 thine electronics, inc. all rights reserved 10 thine electronics, inc. THC63LVDF84B/thc63lvdf64b _rev2.0 notes to users: 1. the contents of this data sheet are subject to change without prior notice. 2. circuit diagrams shown in this data sheet are examples of application. therefore, please pay sufficient attention when designing circuits. even if there are incorrect descriptions, we are not responsible for any problem due to them. please note that incorrect descriptions sometimes cannot be corrected immediately if found. 3. our copyright and know-how are included in this data sheet. duplication of the data sheet and disclosure to other persons are strictly prohibited without our permission. 4. we are not responsible for any problems of industrial proprietorship occurring during THC63LVDF84B/ thc63lvdf64b use, except for those directly related to THC63LVDF84B/thc63lvdf64b?s structure, manu- facture or functions. THC63LVDF84B/thc63lvdf64b is designed on the premise that it should be used for ordi- nary electronic devices. therefore, it shall not be used for applications that require extremely high-reliability (space equipment, nuclear control equipment, medical equipment that affects people?s lives, etc.). in addition, when using THC63LVDF84B/thc63lvdf64b for traffic signals, safety devices and control/safety units in transportation equipment, etc., appropriate measures should be taken. 5. we are making the utmost effort to improve the quality and reliability of our products. however, there is a very slight possibility of failure in semiconductor devices. to avoid damage to social or official organizations, much care should be taken to provide sufficient redundancy and fail-safe design. 6. no radiation-hardened design is incorporated in THC63LVDF84B/thc63lvdf64b. 7. judgment on whether THC63LVDF84B/thc63lvdf64b comes under strategic products prescribed by the for- eign exchange and foreign trade control law is the user?s responsibility. 8. this technical document was provisionally created during development of THC63LVDF84B/thc63lvdf64b, so there is a possibility of differences between it and the product?s final specifications. when designing circuits using THC63LVDF84B/thc63lvdf64b, be sure to refer to the final technical documents. thine electronics, inc. wakamatsu bldg, 6f 3-3-6, nihombashi-honcho, chuo-ku, tokyo, 103-0023 japan tel: 81-3-3270-0666 fax: 81-3-3270-0688
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